View SDA2516-5_1783574.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

circuit description i 2 c bus interface the i 2 c bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. it consists of a serial data line sda and a serial clock line scl. the data line requires an external pull-up resistor to v cc (open drain output stage). the possible operational states of the i 2 c bus are shown in figure 1 . in the quiescent state, both lines sda and scl are high, i.e. the output stage of the data line is disabled. as long a scl remains "1", information changes on the data bus indicate the start or the end of data transfer between two components. the transition on sda from "1" to "0" is a start condition, the transition from "0" to "1" a stop condition. during a data transfer the information on the data bus will only change while the clock line scl is "0". the information on sda is valid as long as scl is "1". in conjunction with an i 2 c bus system, the memory component can operate as a receiver and as a transmitter (slave receiver or slave transmitter). between a start and stop condition, information is always transmitted in byte-organized form. between the trailing edge of the eighth clock pulse and nonvolatile memory 1-kbit e 2 prom preliminary data mos ic p-dip-8-1 features l word-organized reprogrammable nonvolatile memory in n-channel floating-gate technology (e 2 prom) l 128 8-bit organization l supply voltage 5 v l serial 2-line bus for data input and output ( i 2 c bus) l reprogramming mode, 10 ms erase/write cycle l reprogramming by means of on-chip control (without external control) l check for end of programming process l data retention > 10 years l more than 10 4 reprogramming cycles per address l compatible with sda 2516. exception: conditions for total erase and current consumption i cc . type ordering code package sda 2516-5 q67100-h5092 p-dip-8-1 semiconductor group 5 07.94 sda 2516-5
semiconductor group 6 sda 2516-5 a ninth acknowledge clock pulse, the memory component sets the sda line to low as a confirmation of reception, if the chip select conditions have been met. during the output of data, the data output of the memory is high in impedance during the ninth clock pulse (acknowledge master). the signal timing required for the operation of the i 2 c bus is summarized in figure 2 . control functions of the i 2 c bus the memory component is controlled by the controller (master) via the i 2 c bus in two operating modes: read-out cycle, and reprogramming cycle, including erase and write to a memory address. in both operating modes, the controller, as transmitter, has to provide 3 bytes and an additional acknowledge clock pulse to the bus after the start condition. during a memory read, at least nine additional clock pulses are required to accept the data from the memory and the acknowledge master, before the stop condition may follow. in the case of programming, the active programming process is only started by the stop condition after data input (see figure 3). the chip select word contains the 3 chip select bits cs0, cs1 and cs2, thus allowing 8 memory chips to be connected in parallel. chip select is achieved when the three control bits logically correspond to the selected conditions at the select inputs. check for end of programming or abortion of programming process if the chip is addressed during active reprogramming by entering cs/e, the programming process is terminated. if, however, it is addressed by entering cs/a, the entry will be ignored. only after programming has been terminated will the chip respond to cs/a. this allows the user to check whether the end of the programming process has been reached (see figure 3). memory read after the input of the first two control words cs/e and wa, the resetting of the start condition and the input of a third control word cs/a, the memory is set ready to read. during acknowledge clock nine, the memory information is transferred in parallel mode to the shift register. subsequent to the trailing edge of the acknowledge clock, the data output is low impedance and the first data bit can be sampled, (see figure 4 ). with every shift clock, an additional bit reaches the output. after reading a byte, the internal address counter is automatically incremented when the master receiver switches the data line to low during the ninth clock (acknowledge master). any number of memory locations can thus be read one after the other. at address 128, an overflow to address 0 is not initiated. with the stop condition, the data output returns to high-impedance mode. the internal sequence control of the memory component is reset from the read to the quiescent with the stop condition.
semiconductor group 7 sda 2516-5 memory reprogramming the reprogramming cycle of a memory word comprises an erase and a subsequent write process. during erase, all eight bits of the selected word are set into "1" state. during write, "0" states are generated according to the information in the internal data register, i.e. according to the third input control word. after the 27th and the last clock of the control word input, the active programming process is started by the stop condition. the active reprogramming process is executed under onchip control. the time required for reprogramming depends on component deviation and data patterns. therefore, with rated supply voltage, the erase/write process extends over max. 20 ms, or more typically, 10 ms. in the case of data word input without write request (write request is defined as data bit in data register set to 0), the write process is suppressed and the programming time is shortened. during a subsequent programming of an already erased memory address, the erase process is suppressed again, so that the reprogramming time is also shortened. important: switch-on mode and chip reset after the supply voltage v dd has been connected, the data output will be in the high-impedance mode. as a rule, the first operating mode to be entered, should be the read process of a word address. as a result of the built-in power-on reset circuit, programming requests will not be accepted immediately after the supply voltage has been switched on. total erase enter the control word cs/e, load the address register with address 0 and the data register with ff (hex) to erase the entire contents of the memory. switch input cs2 to open immediately prior to generating the stop condition. the subsequent stop condition triggers a total erase. upon termination of total erase, cs2 must be reconnected to either 0 v or 3 4.5 v.
semiconductor group 8 sda 2516-5 pin configuration (top view) pin definitions and functions pin no. symbol function 1 v ss ground 2 cs0 chip select 3 cs1 chip select 4 cs2 chip select 0 v i 0.2 v ; 4.5 v i v cc , open, total erase condition 5 sda data line 6 scl clock line 7 tp test pin 8 v cc supply voltage
semiconductor group 9 sda 2516-5 block diagram
semiconductor group 10 sda 2516-5 absolute maximum ratings parameter symbol limit values unit min. max. supply voltage v cc C 0.3 6 v input voltage v i C 0.3 6 v power dissipation p d 130 mw storage temperature t stg C 40 125 ?c thermal resistance (system-air) r th sa 100 k/w junction temperature t j 85 ?c operating range supply voltage v cc 4.75 5.25 v ambient temperature t a 070?c
semiconductor group 11 sda 2516-5 characteristics t a = 25 ?c parameter symbol limit values unit test condition min. typ. max. supply voltage v cc 4.75 5.0 5.25 v supply current i cc 20 ma v cc = 5.25 v inputs input voltages sda/scl v il 1.5 v input voltages sda/scl v ih 3.0 v cc v input currents sda/scl i h 10 m a v ih = v cc outputs output current sda i ql 3.0 ma v ql = 0.4 v leakage current sda i qh 10 m a v qh = v cc max inputs input voltages cs0/cs1/cs2 v il 0.2 v input voltages cs0/cs1/cs2 v ih 4.5 v cc v input currents cs0/cs1/cs2 i ih 100 m a v cc = 5.25 v clock frequency f scl 100 khz reprogramming duration t prog 10 20 ms erase and write input capacity c i 10 pf total erase t gl 20 ms cs2 = open
semiconductor group 12 sda 2516-5 application circuit application circuit
semiconductor group 13 sda 2516-5 operation states of the i 2 c bus figure 1 read access short form
semiconductor group 14 sda 2516-5 figure 2 timing conditions for the i 2 c bus (high-speed mode) *) note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of scl. parameter symbol limit values unit min. max. minimum time the bus must be free before a new transmission can start t buf 4.7 m s start condition hold time t hd; sta 4.0 m s clock low period t low 4.7 m s clock high period t high 4.0 m s start condition set-up time, only valid for repeated start code t su; sta 4.7 m s data set-up time t su; dat 250 ns rise time of both the sda- and scl-line t r 1 m s fall time of both the sda- and scl-line t f 300 ns stop condition set-up time t su; spo 4.7 m s hold time data t hd; dat 0*)
semiconductor group 15 sda 2516-5 figure 3 programming control word input figure 4 read control word input read a) complete (with word address input) st cs/e as wa as de as sp (the reprogramming starts after this stop condition) st cs/a as check for program end by 1. when as = 1 programming is not finished 2. when as = 0 programming is finished program interruption by st cs/e as st cs/e as wa as st cs/a as da am da am sp n bytes last byte automatic incrementation of the word address st cs/a as da am da am sp b) shortened: bit 0 7 the last adapted word address keep unchanged n bytes last byte autoincrement am = 0 before stop condition am = 1
semiconductor group 16 sda 2516-5 control word table control word input key clock no. 123456789 (acknowledge) cs/e cs/a wa de da 1010cs2cs1cs000 1010cs2cs1cs010 0 a6a5a4a3a2a1a00 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0/1 through memory through memory through memory through memory through master cs/e chip select for data input into memory cs/a chip select for data output out of memory wa memory word address de data word for memory da data word read out of memory d0 to d7 data bits st start condition sp stop condition as acknowledge bit from memory am acknowledge bit from master cs0/cs1/cs2 chip select bits a0 to a6 memory word address bits

▲Up To Search▲

Price & Availability of SDA2516-5

	To Download SDA2516-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .